MB86613S Datasheet, PDF (60/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
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16 15
0
spd tag chanNum tCodeA
sy
dataLength
block data
Fig. 4.15 Asynchronous Stream Packet
Bit
----
1- bit
Field Name
--------------
srcBusID
description
----------------------------------------------------
”0h” :Set ”3FFh” for the bus number in source ID field.
”1h” : Set the value specified in NodeID.busNumber field for the bus number.
3- bit spd
Set the transfer speed:
”000b” : 100Mbps
”001b” : 200Mbps
”010b” : 400Mbps
6- bit tLabel
Set the tLabel (transaction label).
2- bit rt
Set the rt (retry) code. However, the chip does not support the dual- phase
retry. So, always set ”01b” (retryX) in this field.
4- bit tCode
Set the tcode (transaction code).
16- bit destinationID
Set the bus number in the upper 10- bit field and set the node number to transmit
the packet in the lower 6- bit field.
48- bit destinationOffset Set the address to transmit the packet.
16- bit dataLength
Set the byte count of block data section for the transmit packet.
16- bit extendedTcode Set the code that clarifies the lock request/response packet format.
4- bit rCode
Set the rcode (response code).
2- bit tag
Set the tag code that clarifies the format of transmit isochronous data.
6- bit chanNum
Set the channel number of transmit isochronous data.
4- bit sy
Set the sync bit.
4.2. Asynchronous Receive
4.2.1. Program Analysis
Context program is analyzed by the following procedures:
P1 . . . . Store the received packet from the address specified in the descriptor’s dataAddress field to the host
memory in order. If the packet is the last data to be stored, go to the procedure P2. When the host
memory has no space to store any more packet(s) while packets are stored in it (resCount=0), go to
the interrupt handling process.
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