MB86613S Datasheet, PDF (7/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
2.3. Pin Function
2.3.1. PCI Bus Interface
Notes:
I/O denotes input/output pin.
O denotes output pin.
I denotes input pin.
OD denotes open- drain output pin.
Name of pin
PCICLK
RST#
AD31 : 0
C/BE3# : 0#
PAR
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
REQ#
GNT#
PERR#
SERR#
INTA#
I/O
Function
I
PCI bus clock input pin (Max. 33MHz)
I
System reset input pin.
I/O
32- bit PCI Address/Data multiplexed pins.
I/O
PCI Bus Command / Byte Enable multiplexed pins.
I/O
Even Parity pin for AD31:0 and C/BE3#:0#. This pin state becomes valid after 1 PCICLK.
I/O
Frame signal pin that indicates the PCI bus is driven by the master.
I/O
Data Ready signal pin for bus master device.
I/O
Data Ready signal pin for target device.
I/O
Stop signal pin for the data transfer from target to master.
I
Chip select pin to access the configuration register.
Device select pin. While the device is a target, this pin outputs the select signal that indicates
I/O
the self device is selected. While the device is a master, this pin functions as an input pin to
indicate that a device on the bus is selected.
O
Request signal output pin to the bus arbiter to request for the PCI bus use.
I
Grant signal input pin from the bus arbiter to receive the response to the REQ# signal.
I/O
Data Parity Error input/output pin.
OD
Address Parity Error output pin. (Open- drain type output pin.)
OD
Interrupt output pin. (Open- drain type output pin.)
PME#
O
PCI power management enable
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