MB86613S Datasheet, PDF (39/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
31
24 23
16 15
87
0
masterIntEnable
lockRespErr
softInterrupt
ack_tardy
phyRegRecv
postedWriteErr
isochRx
isochTx
RSPkt
cycleTooLong
selfIDComplete2
RQPkt
unrecoverableError
cycleInconsistent
cycleLost
cycle64Seconds
selfIDComplete
busReset
regAccessFail
phy
cycleSynch
ARRS
ARRQ
respTxComplete
reqTxComplete
Bit
----
31
Field Name
rscu
-------------- ----
masterIntEnable rsc
reset
--------
0b
description
------------------------------------------
When this bit state is ”1”, the INTA# signal is active at
the interrupt generation. The effective interrupts must be
set in the bits 26:0 in this register.
When this bit state is ”0”, the INTA# signal is not active
even if any interrupts occur.
29:0 interruptevents
rsc undefined These bits are assigned to the maskable interrupt source.
For each interrupt source, see section 3.2.16.
3.2.18. IsoXmitIntEvent/Mask
This register indicates the result of each context program operation for IT- CPC. When the context program
process completed and ” i ” field at context program is set to ”11b”, the applied channel indicates ”1”.
IntEvent.isochXmit bit indicates the OR operation output with each bit in this register.
Also, the register read value from the IsoXmitIntEventClear indicates AND operation output between the
IsoXmitIntEvent register and IsoRecvIntMask register.
31
24 23
16 15
87
0
isoXmit30
isoXmit31
........................................................................................
isoXmit0
isoXmit1
Bit
----
31:4
3:0
Field Name
rscu
-------------- ----
isoXmit31:4
r
isoXmit3:0
rscu
reset
description
-------- ------------------------------------------
000_0000h Since the device contains only 4channels of context
program controller, these bits are fixed with ”0”.
undefined Each controller processes the context program and ”1” is
indicated in the corresponding bit when the isochronous
packet is completely sent out.
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