MB86613S Datasheet, PDF (46/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
3.2.28. Physical Upper Bound
This register specifies the offset address range for a physical request packet. When the offset address range
for the received packet is from 48’h”0000_0000_0000” to 48’hphysUpperBoundOffset register value
(32- bit)_0000” - 1, the packet is considered as a physical request packet. The maximum offset value set in
this register is ”0001_0000h”.
This register contains the previous value when software reset (HCControl.softReset) is done.
31
24 23
16 15
87
0
physUpperBoundOffset
Bit
----
31:0
Field Name
--------------
physUpper
BoundOffset
rwu
----
rw
reset
--------
0001_
0000h
description
------------------------------------------
These bits specify the upper 32- bit of the offset address
that recognizes the phy request packet.
3.2.29. AT ContextControl
This register is used for controlling the AT- CPC. This register is prepared for request and response packets
individually.
31
24 23
16 15
87
0
eventcode
active
dead
wake
run
Bit
----
15
12
11
10
4:0
Field Name
rscu
-------------- ----
run
rscu
wake
rsu
dead
ru
active
ru
eventcode
ru
reset
--------
0b
description
------------------------------------------
Specifying ”1” at this bit runs the context program
controller (AT- CPC).
undefined Specifying ”1” at this bit wakes up the context program
controller to restart the process.
0b
This bit indicates ”1” when the context program controller
can not proceed the operation because an error occurred.
0b
This bit indicates ”1” when the context program controller
is in- process.
undefined These bits contain the result of context program process.
3.2.30. AT DMA CommandPtr
This register specifies the start address of host memory where the first context program is contained and the
number of descriptor. Set this register when ATContextControl.run bit and .active bit are cleared.
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