MB86613S Datasheet, PDF (94/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
7. PCI Interface
7.1. Alignment
When a data length of received isochronous packet is not a multiple of ”4”, there can be an invalid field in the
last data section. To connect the next packet data with this invalid field and store the data into a host memory is
so called Alignment process. Figure 7.1 shows some examples of Alignment. In Alignment- 1 in the example,
the last byte data in the received packet is stored in bit7:0 field in the host memory. If the next packet is stored
connecting the previously received data, the head data (byte0) in the next packet is stored in bit15:8 in the host
memory. Then, byte3 is stored in the bit7:0 in the next address.
memory
byte3
LSB
byte0
byte0
byte1
byte1
byte2
byte2
byte3
Alignment Example - 1
MSB
memory
byte2
LSB
byte0
byte3
byte1
byte0
byte2
byte1
byte3
Alignment Example - 2
MSB
memory
byte1
LSB
byte0
byte2
byte1
byte3
byte2
byte0
byte3
Alignment Example - 3
MSB
memory
byte0
LSB
byte0
byte1
byte1
byte2
byte2
byte3
byte3
No Alignment
MSB
Fig. 7.1 Examples of Alignment
7.2. Byte Swap Dealing
Because of a different type in endian between 1394 interface and PCI bus interface, a byte order swapping is
required when transmitting a packet from PCI (little- endian) to 1394 (big- endian) bus and receiving a packet
vice versa.
The byte swap is enable only when HCControl.noByteSwapData is cleared or PCI_HCIControl.PCI_Glob-
al_Swap is set. The byte swap deal is not applicable to the packet header (quadlet data in Figure 7.3 is ex-
cluded.) and PHY packet.
memory
byte3
byte2
byte1
byte1
FIFO
lsb
byte0
byte1
byte2
byte3
msb
Fig. 7.2 Byte Swap Dealing
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