MB86613S Datasheet, PDF (79/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
5. LINK
5.1. Generation of Acknowledge Code
The following table lists the acknowledge codes automatically reported when the LINK receives an asynchro-
nous packet. The acknowledge code is basically reported only when HCControl.linkEnable bit is set.
acknowledge name
-----------------
ack_complete
ack_pending
ack_busy_x
ack_data_error
ack_type_error
ack_tardy
code
----
01h
02h
04h
0Dh
0Eh
0Bh
description
---------------------------------------------------
When and asynchronous response packet was received.
When a physical write request packet was received at which
HCControl.PostedWriteEnable bit was set and also PostedWrite
Address register was not full.
When a physical write request packet was received at which
HCControl.PostedWriteEnable bit was cleared.
When a physical read packet was received.
When a packet was received while the FIFO was full.
When a physical write request packet was received at which Posted
WriteAddress register was full.
When a data length error occurred.
When a data CRC error occurred.
When a tcode error occurred.
When a byte count specified in the dataLength field of the received
block write request packet was larger than a byte count specified in
the max_rec field of the 1394 configuration ROM.
When a request packet to the bus management CSR was not either
quadlet lock request or quadlet read request packet.
When a request packet to the 1394 configuration ROM was not the
quadlet read request packet.
When a packet was received while the sytem power was off.
5.2. Open HCI - 1394 Packet Format Conversion
LINK- Tx transmits a packet in the FIFO converting its packet format from Open HCI format to 1394 format.
LINK- Rx receives a 1394 formatted packet and stores in the FIFO after converting its format to Open HCI’s.
For details, please see sections 4.1.3, 4.2.4., 4.3.4, and 4.4.4.
(1) Packet Transmit
a) PHY packet :
- Identify the spd code from the 1st quadlet data.
- Transmit the 2nd and 3rd quadlet data.
b) asynchronous packet:
- Identify the spd code and srcBusID code from the 1st quadlet data.
- Replace the destination ID contained in the 2nd quadlet data with bit31- bit16 code of the 1st quadlet
data.
- Set the sourceID which is composed of bus number and node number determined with the previously
mentioned srcBusID in a field where the destinationID of 2nd quadlet data is located.
78