MB86613S Datasheet, PDF (88/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
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24 23
16 15
87
0
00
phy_ID
00 type
logical inverse of first quadlet
Bit
----
6
4
Fig. 6.9 resume packet Format
Field Name
--------------
phy_ID
description
------------------------------------------
This bit indicates the node number of the place from which a packet is
transmitted.
type
”0Fh” : resume packet.
6.2. Device Reset
MB86613S device has three types of reset as follows:
1) Hardware Reset (Power- on Reset) :
Input ”L” level of signal to the RST pin of device.
This reset makes all the functions to stop and initializes all the registers.
2) Software Reset :
Set HCControl.softReset bit.
This reset stops LINK, CPCs, and PCI operations. But PHY still functions and that retains the bus
topology configured.
A part of registers is not initialized by the software reset.
3) Bus Reset :
Set IBR bit of PHY register.
This reset does not affect to all the device functionalities, except for the MB86613S’s internal bus
management CSR register which is initialized by the reset.
The MB86613S device contains a power- on reset circuit in order to allow the device operate in a 1394 cable
power while the system power is shut- down. Figure 6.1 shows the block diagram of circuit. This circuit auto-
matically resets the device when detecting a 1394 cable power while the system power is shut- down.
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