MB86613S Datasheet, PDF (61/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
P2 . . . . Set the interrupt event code and remained byte count of host memory in the descriptor’s xferStatus
and resCount fields. Then, set the IntEvent.RQPkt or RSPkt.
After the process is completed, go to the interrupt handling process if no host memory space is
available. If the memory has the space, repeat the procedure P1.
The way to store the packet follows buffer- fill mode only. For details, see section 4.2.3 Buffer- Fill Mode.
last data
P1
reqCount=0
reqCount ¹ 0
P2
reqCount=0
INT
Fig. 4.16 State Machine of Program Analysis for Asynchronous Packet Receive
4.2.2. Interrupt Handle
There are a number of interrupts possibly occur in the asynchronous receive. The following lists the error
name, code, and the condition:
Also, it is assumed that interrupt reported every packet received is handled in statemachine P2 in Fig. 4.16.
(1) evt_no_status : 00h
when receiving PHY packet.
(2) evt_descriptor_read : 06h
when a PCI bus error occurs while the context program moves from the host memory into the work RAM.
(3) evt_unknown : 0Eh
when the descriptor in the context program can not be processed due to some error or problem.
(4) evt_data_write : 08h
when a PCI bus error occurs while the packet data is written from AR- FIFO to host memory.
(5) evt_bus_reset : 09h
when the bus reset occurs and the bus reset packet generated is stored in AR- FIFO.
(6) ack_data_error : 1Dh
when a dataCRC error or data length error occurs on the received packet.
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