MB86613S Datasheet, PDF (36/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
3.2.14. Self ID Count
This register indicates the status information with regard to self ID packet at a bus reset. selfIDSize field is
cleared by the bus reset.
31
24 23
16 15
87
0
selfIDGeneration
selfIDSize
selfIDError
Bit
----
31
Field Name
rwu
-------------- ----
selfIDError
ru
23:16 selfIDGeneration ru
12:2 selfIDSize
ru
reset
--------
undefined
description
------------------------------------------
This bit indicates ”1” when an error occurs while the
received self ID packet is stored in the host memory.
undefined These are selfID generation counter that increments every
bus reset detected.
undefined These bits indicate the size of received self ID packet in
quadlet unit.
3.2.15. IRMultiChanMask
This register is used for setting the channel of packet when isochronous packet with multiple channels is re-
ceived. This register is valid only when IRContextControl.multiChanMode bit is set. Also, only one channel
out of 4 channels of IR- CPC can be used. If multiple channels are set with their IRContextControl.multiChan-
Mode bit, The priority is made to channel 0 in order. Using this register requires the IRContextControl.buffer-
Fill and isochHeader bits to be set. Also, the IRContextMatch.channelNumber filed is invalid.
31
24 23
16 15
87
0
isoChannel62
isoChannel63
31
........................................................................................
24 23
16 15
87
isoChannel32
isoChannel33
0
Bit
----
31:0
isoChannel30
........................................................................................
isoChannel0
isoChannel1
isoChannel31
Field Name
rscu
-------------- ----
isoChannelN
rsc
reset
--------
undefined
description
------------------------------------------
N denotes the channel number.
When IRContextControl.multiChanMode is set, the
isochronous packet on the channel being specified with
this register is received.
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