MB86613S Datasheet, PDF (49/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
10
active
4:0 eventcode
ru
0b
This bit indicates ”1” when the context program controller
is in- process.
ru
undefined These bits contain the result of context program process.
3.2.34. IT DMA CommandPtr
This register specifies the start address of host memory where the first context program is contained and the
number of descriptor. Set this register when ITContextControl.run bit and .active bit are cleared.
The context program can be composed of maximum 8 descriptors. However, because the descriptor to speci-
fy the packet header needs 32- byte program, please set ”2h” to ”8h” in the Z field.
When an error occurred while processing the context program, the descriptor address field indicates the start
address in the host memory where the descriptor that was processed is contained. When the context pro-
gram is normally completed, the address field indicates the host memory start address where the last pro-
cessed descriptor is contained and Z field indicates ”0”.
31
24 23
16 15
87
0
descriptorAddress[31:4]
Z
Bit
----
31:4
3:0
Field Name
rwu
-------------- ----
descriptorAddress rwu
Z
rwu
reset
--------
undefined
description
------------------------------------------
Specify the start address for the memory where the first
context program is stored. (16- byte boundary)
undefined Specify the number of descriptor that forms the context
program.
3.2.35. IR ContextControl
This register is used for controlling the IR- CPC. This register is prepared for 4 context programs individually.
Set bufferFill, isochHeader, cycleMatchEnable, and multiChanMode bits when
IRContextControl.run bit .active bit are cleared. When multiChanMode bit is set, please make sure to set the
bufferFill and isochHeader bits too. In this case, the device ignores the IRContextMatch.channelNumber
field. cycleMatchEnable bit is cleared when the IRContextControl.active bit is set.
multiChanMode and bufferFill bits are cleared when dualBufferMode bit is set.
31
24 23
dualBufferMode
multiChanMode
cycleMatchEnable
isochHeader
bufferFill
16 15
87
0
eventcode
active
spd
dead
wake
run
Bit
----
31
48
Field Name
rscu
-------------- ----
bufferFill
rsc
reset
--------
undefined
description
------------------------------------------
”1” at this bit indicates that the packet received in buffer-
fill- mode is stored in the memory.
”0” at this bit indicates that the packet received in packet-
per- buffer- mode is stored in the memory.