MB86613S Datasheet, PDF (33/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
3.2.9. Configuration ROM Mapping
This register specifies the base address for the 1394 configuration ROM space. However, since the first
20- byte (offset: FFFF_F000_0400- 0410h) in the ROM is built in the MB86613S, the specified value in this
register has no meaning. The base address must be set to this register before setting the HCControl.linkEn-
able bit.
31
24 23
16 15
87
0
configROMaddr
Bit
Field Name
rwu
---- -------------- ----
31:10 configROMaddr rw
reset
--------
undefined
description
------------------------------------------
Specify the base address of 1394 configuration ROM in
1024- byte boundary.
3.2.10. PostedWriteAddress
This register is used for storing and indicating the packet source ID and destinationOffset if a host bus error
occurs while the payload data for received physical write request packet is storing into a host memory.
This register is valid only when the HCControl.postedWriteEnable bit is set.
The structure of register is 4 FIFOs.
When a host bus error occurs, this register stores the packet source ID and destination offset. After that, IntE-
vent.PostedWriteErr bit is set. Software needs to take the following steps when the IntEvent.PostedWriteErr
bit is set:
1) Read out the PostedWriteAddress_Hi register.
2) Read out the PostedWriteAddress_Lo register.
3) Clear the IntEvent.PostedWriteErr bit.
If the IntEvent.PostedWriteErr bit is still set, take the above steps repeatedly.
31
24 23
sourceID
16 15
87
0
offsetHi
Bit
Field Name
rwu
---- -------------- ----
31:16 sourceID
ru
15:0 offsetHi
ru
reset
--------
undefined
description
------------------------------------------
Stores the source ID written in the packet that caused
an error during the physical write request packet receive.
undefined Stores the upper 16- bit of offset_address written in the
packet that caused an error during the packet receive.
32