MB86613S Datasheet, PDF (131/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
Annex 1.1.1. PacketControl Register
This register manages the LINK state or sets the operation mode when a PHY packet is received. Refer to 5.4
“Physical Configuration Packet Receive” for the use of autoPhyPkt bit.
31
24 23
16 15
87
0
8KHzSource
checkPhyPkt
rcvBRPkt
concatinate
autoExtPkt
autoPhyPkt
autoLinkPkt1
autoPingPkt
Bit
----
23
9
8
7
4
2
1
0
Field Name
rscu
-------------- ----
8KHzSource
rsc
checkPhyPkt
rsc
rcvBRPkt
rsc
contcatinate
rsc
autoExtPkt
rsc
autoPingPkt
rsc
autoLinkPkt
rsc
autoPhyPkt
rsc
reset
--------
0b
description
------------------------------------------
This bit is valid only when LinkControl.cycleSource bit is
set. Setting ”1” at this bit increments the IsoCycleTimer.
cycleCount field by the 8KHz clock(CSCLK) input from the
external. Setting”0” at this bit increments the IsoCycle
Timer.cycleCount field by the 8KHz clock generated by the
24.576MHz.
0b
Setting ”1” at this bit allows to check the logical inverse
section of the received PHY packet.
1b
Setting ”1” at this bit generates a bus reset packet.
0b
Setting “1” at this field concatinates two or more packets
when they are transmitted.
1b
Setting ”1” at this bit automatically reports a remote reply
packet or a remote confirmation packet when receiving the
remote access packet or a remote command packet.
1b
Setting ”1” at this bit transmits a self ID packet when
receiving a ping packet.
0b
Setting ”1” at this bit enables LINK packet transmit and
receive after receiving a link on packet.
Setting ”0” at this bit enables LINK packet transmit and
receive even if no link on packet is received. (But it
requires HCControl.linkEnable bit to be set.)
0b
Setting ”1” at this bit replaces the Gap_count and RHB
fields in PHY register when receiving a phy configuration
packet.
Setting ”0” at this bit does not replace the PHY register
values when receiving a phy configuration packet.
130