MB86613S Datasheet, PDF (69/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
(4) evt_data_write : 08h
when a PCI bus error occurs while the data is put into the xferStatus and timeStamp sections in the descriptor,
or when a PCI bus error occurs while the STORE_VALUE command is executed.
(5) evt_tcode_err : 0Bh
when the tcode for the transmit packet is not Ah. (This case, no packet is transmitted.)
(6) evt_underrun : 04h
when the IT- FIFO becomes empty while transmitting the packet. (or when the PCI bus error occurs while
transmitting the packet.)
(7) ack_complete : 11h
when a packet is completely transmitted.
The following describes and shows the state machine of interrupt handling:
I1 . . . . Set the interrupt event code in the ITContextControl.eventcode field and then further set the event
codeand cycle timer value in the xferStatus and timeStamp sections in the last descriptor if the ’ s’ flag
in thelast descriptor is ”1b”. After completing these processes, go to the procedure I3 if the context
programprocessed normally. If the process is not done normally, go to the procedure I2.
I2 . . . . Clear the FIFO contents and set the IntEvent.unrecoverableError bit if the ’ i ’ flag in the last descriptor
indicates ’11b’. Then, return to the START after writing the start address of host memory where the
erroneous descriptor is stored to the CommandPtr.descriptorAddress.
I3 . . . . If the ’ i ’ flag in the last descriptor indicates ’11b’ or ’01b’, set the IntEvent.isoXmitN field.
After that, if ’Z’ field indicates ”0” in the last descriptor then go to the START. If it indicates ”1” or more,
then store the address set in the branchAddress field of the last descriptor in the CommandPtr.
descriptorAddress field and go to the program loading process.
If the packet can not be transmitted due to an error occurred during the program process, the context program
which is stored in the host memory where the address is specified in the first descriptor’s skipAddress is exe-
cuted. This is related with Cycle Loss function noted in section 4.3.3.
(1), (2), (3),
(4), (6)
I1
(5), (7)
I2
z=0
I3
z>0
START
LOAD
Fig. 4.30 State Machine of Interrupt Handle for Isochronous Packet Transmit
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