MB86613S Datasheet, PDF (17/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
3.1.4. Status
This register holds event status on PCI interface. When any of events occurred, please clear the bit corre-
sponding to the event by writing ”1” at that bit.
31
24 23
16
Bit
----
31
fast_target
PERR_asserted
DEVSEL_time
target_abort
master_abort
SERR_asserted
parity_err_detected
Capabilities_List
Field Name
rwcu
-------------- ----
parity_err_detected rcu
reset
description
-------- ------------------------------------------
0b
This bit indicates ”1” when a parity error occurs.
30
SERR_asserted rcu 0b
This bit indicates ”1” when a system error occurs.
29
master_abort
rcu 0b
This bit indicates ”1” when detecting the master- abort
and the transfer stops.
28
target_abort
rcu 0b
This bit indicates ”1” when detecting the target- abort
and the transfer is stopped.
26:25 DEVSEL_time
r
01b
Read out value from this bit is ”01h”. The contents of the
bits reacts within 2 PCICLK after FRAME# asserted.
24
PERR_asserted rcu 0b
This bit indicates ”1” when a parity error is detected, that is,
when ’Command.parity_enable’ bit is set and PERR#
signal is output or PERR# is detected.
23
fast_target
r
1b
This bit indicates ”1” because the device supports the
high- speed back- to- back transfer.
20
Capabilities_List r
1b
This bit indicates ”1” because the device supports the
PCI bus power management.
3.1.5. Revision ID
Bit
----
7:0
Field Name
rwcu
-------------- ----
revision
r
reset
description
-------- ------------------------------------------
00h
This bit indicates the device revision ID. It is ”00h”.
3.1.6. Class Code
This register is used for identifying the MB86613S functions and programming interface. Each class code is
read only field that displays the functional and programming interface information.
31
24 23
16 15
8
base_class
sub_class
prog_if
16