MB86613S Datasheet, PDF (78/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
6- bit chanNum
Indicates the channel of isochronous data received.
4- bit tCode
Indicates the tcode (transaction code).
4- bit sy
Indicates the sync bit code.
4.5. Physical Request
When the chip receives a request packet for the address listed below, it is handled as a physical request pack-
et. This packet is not stored in the host memory and the AR- CPC and AT- CPC will take the following actions
automatically:
(1) physical memory : 0000_0000_0000h - PhysicalUpperBound register value (32- bit)+0000h
a) quadlet read request:
The host memory address is determined as the lower 32- bit of offset address for the received packet.
1 quadlet data in the host memory indicated by that address is handled as the quadlet data for the quadlet
read response (tcode=8h) and the response packet is transmitted.
b) block read request :
The host memory address is determined as the lower 32- bit of offset address for the received packet.
Based on that address, some byte data as specified in the dataLength field are handled as the block data
for the block read response (tcode=7h) and the response packet is transmitted.
c) quadlet write request :
The host memory address is determined as the lower 32- bit of offset address for the received packet.
The quadlet data are stored in that address.
d) block write request :
The host memory address is determined as the lower 32- bit of offset address for the received packet.
The block data are stored from that address in order.
(2) bus management CSR: FFFF_F000_021Ch - FFFF_F000_0228h
a) quadlet read request :
1 quadlet data of the on- chip bus management CSR is handled as the quadlet read response data
(tcode=8h) and the response packet is transmitted.
b) lock request :
1 quadlet data of the on- chip bus management CSR is compared with the arg_value of the received
packet and the result of comparison is handled as the lock response packet data (tcode=Bh) and the
response packet is transmitted.
(3) configuration ROM : FFFF_F000_0400h - FFFF_F000_07FCh
a) quadlet read request :
1 quadlet data of the 1394 configuration ROM is handled as the quadlet read response data (tcode=8h)
and the response packet is transmitted. However, when the offset address for the received packet is
within FFFF_F000_0400 to _0410, the data in the on- chip ConfigROMHeader, BusID, BusOptions,
GUIDHi, and GUIDLo registers are handled as the quadlet data and the response packet is transmitted.
When the offset address is within FFFF_F000_0414 to _07FC, the address for the 1394 configuration
ROM is calculated from the base address specified in the ConfigROMmapping register and the read out
value is handled as the quadlet data and the response packet is transmitted.
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