MB86613S Datasheet, PDF (38/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
Bit
----
18
Field Name rscu
--------------
regAccessFail rscu
reset
-------
undefined
17
busReset
rscu undefined
16
selfIDComplete rscu undefined
15
selfIDcomplete2rscu undefined
9
lockRespError rscu undefined
8
posted-
rscu undefined
WriteError
7
isochRx
ru
undefined
6
isochTx
ru
undefined
5
RSPkt
rscu undefined
4
RQPkt
rscu undefined
3
ARRS
rscu undefined
2
ARRQ
rscu undefined
1
respTx-
rscu undefined
Complete
0
reqTx-
rscu undefined
Complete
description
---------------------------------------------
This bit indicates”1” when OHCI register access failed
by SCLK missing from PHY.
This bit indicates ”1” when a bus reset is detected.
This bit indicates ”1” when self ID packet was
completely received.
This bit indicates”1” when next self ID packet was
completely received during selfIDComplete is”1”.
This bit indicates ”1” when an acknowledge except
”ack_complete” is received after transmitting the lock
response packet in response to the received lock request
packet.
This bit indicates ”1” when a host bus error occurs while
the received phy write request packet is stored in the host
memory and ack_complete acknowledge has already
been reported.
This bit indicates ”1” when the context program process for
the isochronous- receive is done. For details, see section
3.2.19.
This bit indicates ”1” when the isochronous packet transmit
is done. For details, see section 3.2.18.
This bit indicates ”1” when the received asynchronous
response packet is completely stored in the host memory.
This bit indicates ”1” when the received asynchronous
request packet is completely stored in the host memory.
This bit indicates ”1” when the context program process for
the asynchronous- receive response is done.
This bit indicates ”1” when the context program process for
the asynchronous- receive request is done.
This bit indicates ”1” when the asynchronous response
packet is completely transmitted.
This bit indicates ”1” when the asynchronous request
packet is completely transmitted.
3.2.17. IntMask
This register masks the interrupt event with INTA# signal when an error occurs during the packet receive or
between the device and host memory. The register format is the same as one for the IntEvent register. The
INTA# signal is active when the enabled mask bit and it’s intEvent bit are both ON.
When the IntMask.masterIntEnable bit is cleared, the interrupt mask setting with this register is invalid.
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