MB86613S Datasheet, PDF (37/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
3.2.16. IntEvent
This register indicates the interrupt event for transfer error during the packet transfer or between the device
and host memory. The read value from the IntEventClear register contains the AND operated value between
IntEvent register and IntMask register. The device clears selfIDcomplete bit by setting the IntEvent.busReset
bit at the bus reset. Software must not clear the busReset bit until the selfIDComplete bit contains ”1”.
Also, the interrupt event can be desirably generated by setting the desired bit.
31
24 23
16 15
87
0
softInterrupt
ack_Tardy
phyRegRecv
cycleTooLong
unrecoverableError
cycleInconsistent
cycleLost
cycle64Seconds
cycleSynch
lockRespErr
postedWriteErr
isochRx
selfIDComplete2 _isochTx
selfIDComplete
RSPkt
busReset
RQPkt
regAccessfail
ARRS
phy
ARRQ
respTxComplete
reqTxComplete
Bit
----
29
27
26
Field Name rscu
--------------
softInterrupt rsc
ack_Tardy
rscu
phyRegRecv rscu
reset
-------
undefined
undefined
undefined
25
cycleTooLong rscu undefined
24
unrecoverable- rscu undefined
Error
23
cycle-
rscu undefined
Inconsistent
22
cycleLost
rscu undefined
21
cycle64-
Seconds
rscu undefined
20
cycleSynch rscu undefined
19
phy
rscu undefined
description
---------------------------------------------
Software Interrupt
reserved
This bit indicates ”1” when reading out the PHY register
is completed.
This bit indicates ”1” when the isochronous cycle time
exceeded beyond the allowable time in the cycle master
operation.
This bit indicates ”1” when an unrecoverable error such
as abort the PCI data transfer occurs.
This bit indicates if the received cycle start packet contains
the different data from those in the cycletimer.second and
cycleTimer.count.
This bit indicates ”1” when no cycle start packet was
received or transmitted between two cyclesynch periods.
This bit indicates ”1” every 64 seconds.
This bit indicates ”1” every new isochronous cycle is
detected.
This bit indicates ”1” when the PHY detected the
following interrupt:
1) loop detected interrupt
2) cable power failure detected interrupt
3) arbitration state machine timeout interrupt
4) port event interrupt
Each interrupt register in the PHY register is cleared
after this bit is cleared.
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