MB86613S Datasheet, PDF (42/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
3.2.22. LinkControl
This register controls the on- chip LINK layer, such as the packet process and cycle timer.
CycleSource bit is valid only when cycleMaster bit is enable. CycleMaster bit is cleared only when IntEvent
cycleTooLong bit is set. Also, if the rcvPhyPkt bit and HCControl.linkEnable bit are set, PHY packets (received
phy configuration, link- on, ping packets and so on) are stored in the FIFO.
31
24 23
16 15
87
0
cycleTimerEnable
cycleMaster
rcvSelfID
rcvPhyPkt
tag1SyncFilterLock
Bit
----
21
20
10
9
6
Field Name
rscu
-------------- ----
cycleMaster
rscu
cycleTimerEnable rsc
rcvPhyPkt
rsc
rcvSelfID
rsc
tag1SyncFilterLock rs
reset
--------
undefined
description
------------------------------------------
Cycle master enable bit. Writing ”1” at this bits makes the
device cycle master function.
undefined Specifying ”1” counts up the CycleTimer.cycleOffset by the
24.576MHz clock.
undefined ”1” at this bit receives the the PHY packet in the FIFO.
undefined ”1” at this bit receives the self ID packet in the FIFO.
*
“1” at this bit set the IRContexMatch and tag1SyncFilter bit.
*:this bit is cleared only by hardware reset.
3.2.23. Node Identification and Status
This register indicates a part of data stored in the PHY register. Do not set the Contextcontrol.run bit when the
iDValid bit is cleared.
31
24 23
16 15
87
0
busNumber
nodeNumber
root
iDValid
CPS
41