MB86613S Datasheet, PDF (70/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
4.3.3. Cycle Loss Function
When isochronous packets cannot be transmitted due to a bus reset or cycle lost generated, IT- CPC exe-
cutes the context program stored in the address specified in skipAddress field of the first descriptor. The value
to be specified in the skipAddress field selects how to transmit the packets as follows:
a) When transmitting the next packet (”A” packet) :
Store the start address of context program that handles the next packet in the skipAddress field.
As shown in an example in Figure 4.31, the chip skip the process to the context program that handles the
packet A6 because a bus reset occurred after the completion of process for the packet A4 in cycle 4. However,
the bus reset is continuing in cycle 5 and so the chip goes to the process to the context program for A6. Then,
the chip processes the packet A6 and stores it in IT- FIFO.
b) When transmitting the same packet (”B” packet) :
Store the start address of context program currently in- process in the skipAddress field.
As shown in an example in Figure 4.31, a bus reset occurred after the completion of process for the packet B4
in cycle 4. However, the bus reset is still continuing in cycle 5 where the chip has to handle the packet B5. In
this case, the chip still intends to process the packet B5 to skip the process to the context program for the
packet B5. After that, in fact, the chip processes the packet B5 in cycle 6 and stores the packet in IT- FIFO.
c) When transmitting another packet (”C” packet) :
Store the start address of context program that processes another packet in the skipAddress field.
As shown in an example in Figure 4.31, a bus reset occurred after the completion of process for the packet C4
in cycle 4. However, the bus reset is still continuing in cycle 5 and so, the chip skips to the process of context
program for Cx. Then, it processes the packet Cx in cycle 6, stores the packet in IT- FIFO, and terminates the
process after transmitting the Cx packet onto 1394 bus in cycle 8.
d) When terminating the process (”D” packet) :
Set ”0h” in Z field of skipAddress.
As shown in an example in Figure 4.31, a bus reset occurred after the completion of process for the packet D4
in cycle 4. However, the bus reset is still continuing in cycle 5. Therefore, the chip terminates the process after
transmitting the D4 packet onto 1394 bus in cycle 7.
When an error is detected while transmitting a packet, the chip discards the remained packet in the FIFO and
processes the context program stored in the specified address in skipAddress field.
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