MB86613S Datasheet, PDF (44/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
3.2.25. Isochronous Cycle Timer
This register sets and indicates the cycle timer value that bus manager owns.
When the MB86613S device is a cycle master, the transmit cycle start packet is generated with data set in this
register. In this case, if the cycleCount field is counted by the external CLK (8kHz) using the LinkControl.cycle-
Source bit, cycleOffset field is also counted using the LinkControl.cycleTimerEnable bit, and external clock is
input to the device, then the cycleOffset field is cleared. Also, if no external clock has been input until cycleOff-
set makes 3072 counts, the cycleCount field is not incremented and waits for the external clock input pausing
the cycleOffset count.
When the device is not a cycle master, it stores the received cycle start packet data into this register. In case no
cycle start packet is not coming, the counter keeps its function by continuing the cycleOffset count.
This register contains the previous data when the hardware or software reset(HCControl.softReset) is done.
31
cycleSeconds
24 23
16 15
cycleCount
87
0
cycleOffset
Bit
Field Name
rwu
---- -------------- ----
31:25 cycleSeconds
rwu
24:12 cycleCount
rwu
11:0 cycleOffset
rwu
reset
--------
undefined
description
------------------------------------------
The value in these bits is increment every 8000 counts of
the cycleCount.
undefined
When the LinkControl.cycleSource bit is set to ”1”, these
counter bits are increment by the CSCLK (8kHz).
When the LinkControl.cycleSource bit is set to ”0”. these
counter bits are increment every 3072 counts of
cycleOffset.
undefined These are the cycleOffset bits to manage the 125ms cycle
by 3072 counts using the 24.576MHz clock.
3.2.26. AynchronousRequestFilter
This register functions as a packet filter by referring to the source ID of received asynchronous request packet.
The device stores asynchronous request packet which has the source ID specified in this register. (Any other
asynchronous request packets are not stored and no acknowledge is reported.) asynchronous response
packets and request packets for 1394 configuration ROM and bus management CSR are not applied to the
filtering conditions.
This register (except asynReqResourceAll bit) is cleared by a bus reset.
31
24 23
16 15
87
0
asynReqResource62
........................................................................................
asynReqResource32
asynReqResource33
asynReqResourceAll
43