MB86613S Datasheet, PDF (80/134 Pages) Fujitsu Component Limited. – IEEE1394 Open HCI Controller

Preliminary
c) isochronous packet:
- Identify the spd code from the 1st quadlet data.
- Replace the dataLength value contained in the 2nd quadlet data with the bit31- bit16 code of the 1st
quadlet data.
(2) Packet Receive :
a) PHY packet :
- Insert 1 quadlet data in which tcode ”E”h is set into the head of received packet.
- Insert 1 quadlet trailer data which consists of event code, xferStatus information, and timeStamp value
that indicates the time information on which the packet is stored in the FIFO into the end of received
packet.
b) asynchronous and isochronous packets :
- Insert 1 quadlet trailer data which consists of event code, xferStatus information, and timeStamp value
that indicates the time information on which the packet is stored in the FIFO into the end of received
packet.
c) self ID packet (only when LinkControl.rcvSelfID bit is set) :
- Insert 1 quadlet trailer data which consists of selfIDGeneration indicating the number of bus reset
generation and timestamp value for the received packet into the packet.
- Store the self ID packet following the trailer data into the FIFO.
IR- CPC takes the responsibility to delete the isochronous packet header and trailer data from the received
packet (only when IRContextControl.isochHeader bit is cleared), or to insert a trailer data into the head of
received packet (only when packet- per- buffer mode clearing IRContextControl.bufferFill bit is activating).
5.3. Bus Reset
Upon a generation of bus reset, the chip performs the following processes:
(1) asynchronous packet transmit :
It stops the packet transmit and reports ’evt_flush’ event code. However, if no acknowledge was not able
to receive because the bus reset has occurred after transmitting the packet, ’eve_ack_missing’ is
reported instead.
It also clears the ATContextControl.active bit in order to complete the AT- CPC process clearing all the
packets remained in the AT- FIFO.
(2) isochronous packet transmit :
Stops the packet transmit. If the next packet to be transmitted has already been stored in the IT- FIFO,
the packet transmit is restarted after the completion of bus reset and receiving the cycle start packet.
(3) asynchronous and Isochronous packet receive :
Inserts a bus reset packet into the AR- FIFO as shown in Figure 5.1. This packet is handled as a kind of
PHY packet and the eventcode field in the trailer data contains an event code 09h that is ’evt_bus_reset.
In case the bus reset occurs when the HCControl.linkEnable bit is cleared, the bus reset packet generated and
the selfID packet received are not stored into the FIFO.
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