MC68HC908RK2 Datasheet, PDF (99/158 Pages) Motorola, Inc – Microcontroller Unit

Port B
Figure 9-4 shows the port A I/O logic.
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 9-1 summarizes the operation of the port A pins.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
DDRAx
PTAx
V_DD
KBIEX
INTERNAL
PULLUP
DEVICE
PTAx
READ PTA ($0000)
Figure 9-4. Port A I/O Circuit
Table 9-1. Port A Pin Functions
KBIE⁽²⁾ Bit
DDRA Bit PTA Bit
I/O Pin Mode
Accesses to DDRA
Read/Write
1
X
X⁽¹⁾
Input, V_DD(4)
DDRA[7:0]
0
0
X
Input, Hi-Z⁽⁵⁾
DDRA[7:0]
0
1
X
Output
DDRA[7:0]
Notes:
1. X = Don’t care
2. Keyboard interrupt enable bit (see 7.5.2 Keyboard Interrupt Enable Register)
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to V_DD by internal pullup device
5. Hi-Z = High impedance
Accesses to PTA
Read
Write
Pin
PTA[7:0]⁽³⁾
Pin
PTA[7:0]⁽³⁾
PTA[7:0]
PTA[7:0]
NOTE
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction register.
However, the data direction register bit must be a 0 for software to read the
pin.
9.3 Port B
Port B is a 6-bit special function port that shares three of its pins with the timer (TIM) module and one with
the buffered internal bus clock MCLK.
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
99