MC68HC908RK2 Datasheet, PDF (127/158 Pages) Motorola, Inc – Microcontroller Unit

I/O Signals
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
11.7 I/O Signals
Port B shares three of its pins with the TIM. TCLK can be used as an external clock input to the TIM
prescaler and the TIM channel 0 I/O pin PTB2/TCH0 and TIM channel 1 I/O pin PTB4/TCH1.
11.7.1 TIM Clock Pin (TCLK)
TCLK is an external clock input that can be the clock source for the TIM counter instead of the prescaled
internal bus clock. Select the TCLK input by writing 1s to the three prescaler select bits, PS2–PS0. See
11.8.1 TIM Status and Control Register. The minimum TCLK pulse width, TCLK_LMIN or TCLK_HMIN, is:
1
Bus frequency ^{+ tsu}
The maximum TCLK frequency is:
Bus frequency ÷ 2
Refer to 13.8 Control Timing.
TCLK is available as a general-purpose I/O pin when not used as the TIM clock input. When the TCLK
pin is the TIM clock input, it is an input regardless of the state of the DDRB3 bit in data direction register B.
11.7.2 TIM Channel I/O Pins (TCH0 and TCH1)
The channel I/O pins are programmable independently as an input capture pin or an output compare pin.
TCH0 and TCH1 can be configured as buffered output compare or buffered PWM pins.
11.8 I/O Registers
These I/O registers control and monitor operation of the TIM:
• TIM status and control register, TSC
• TIM control registers, TCNTH and TCNTL
• TIM counter modulo registers, TMODH and TMODL
• TIM channel status and control registers, TSC0 and TSC1
• TIM channel registers, TCH0H, TCH0L, TCH1H, and TCH1L
11.8.1 TIM Status and Control Register
The TIM status and control register (TSC):
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
127