MC68HC908RK2 Datasheet, PDF (68/158 Pages) Motorola, Inc – Microcontroller Unit

Internal Clock Generator Module (ICG)
ICLK). When switching the CS bit, both ICLK and ECLK must be on (ICGON and ECGON set). The clock
being switched to must also be stable (ICGS or ECGS set).
CS
ICLK
ECLK
IOFF
EOFF
RESET
V_SS
SELECT
ICLK
ECLK
IOFF
EOFF
FORCE_I
FORCE_E
OUTPUT
SYNCHRONIZING
DIV2
CLOCK
SWITCHER
CGMXCLK
CGMOUT
NAME
REGISTER BIT
NAME
TOP LEVEL SIGNAL
NAME
MODULE SIGNAL
Figure 6-6. Clock Selection Circuit Block Diagram
6.3.5.2 Clock Switching Circuit
To robustly switch between the internal clock (ICLK) and the external clock (ECLK), the switch assumes
the clocks are completely asynchronous, so a synchronizing circuit is required to make the transition (see
Figure 6-7). When the clock select bit is changed, the switch will continue to operate off the original clock
for between 1 and 2 cycles as the select input transitions through one side of the synchronizer. Next, the
output will be held low for between 1 and 2 cycles of the new clock as the select input transitions through
the other side. Then the output starts switching at the new clock’s frequency. This transition guarantees
that no glitches will be seen on the output even though the select input may change asynchronously to
the clocks. The unpredictably of the transition period is a necessary result of the asynchronicity.
IOFF
ICLK
FORCE_I
D
Q
DFF
CK QB
D
Q
DFF
CK QB
ECLK
FORCE_E
SELECT
CK QB
DFF
D
Q
CK QB
DFF
D
Q
EOFF
FORCE_I = Force internal; reset condition
FORCE_E = Force external
Figure 6-7. Synchronizing Clock Switcher Circuit Diagram
OUTPUT
MC68HC908RK2 Data Sheet, Rev. 5.1
68
Freescale Semiconductor