MC68HC908RK2 Datasheet, PDF (105/158 Pages) Motorola, Inc – Microcontroller Unit

SIM Bus Clock Control and Generation
10.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 10-3. This clock can
come from either an external oscillator or from the internal clock generator (ICG) module.
10.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (ECLK) divided by four or
the ICG output (ICLK) divided by four.
10.2.2 Clock Startup from POR or LVI Reset
When the power-on reset (POR) module or the low-voltage inhibit (LVI) module generates a reset, the
clocks to the CPU and peripherals are inactive and held in an inactive phase until after 4096 CGMXCLK
cycles. The RST pin is driven low by the SIM during this entire period. The bus clocks start upon
completion of the timeout.
ECLK
CLOCK
SELECT
CIRCUIT
÷2
ICLK
ICG
Generator
CS
PTB3
MONITOR MODE
USER MODE
ICG
CGMXCLK
A
CGMOUT
B _S*
*When S = 1,
CGMOUT = B
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
Figure 10-3. ICG Clock Signals
10.2.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM
counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This
timeout is selectable as 4096 or 32 CGMXCLK cycles. (See 10.6.2 Stop Mode.)
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
105