MC68HC908RK2 Datasheet, PDF(79/158 Page) Motorola, Inc

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MC68HC908RK2 Datasheet, PDF (79/158 Pages) Motorola, Inc – Microcontroller Unit

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I/O Registers

Table 6-5. ICG Module Register Bit Interaction Summary

Condition

CMIE CMF CMON CS ICGON ICGS ECGON ECGS N[6:0] TRIM[7:0] DDIV[3:0] DSTG[7:0]

Reset 0

$15

$80

CMF = 1 â (1)

1â

â uw

CMON = 0 0

(0) â â

CMON = 1 â â (1) â 1

â uw

CS = 0 â â â (0) 1

CS = 1 â â â (1) â

ICGON = 0 0

0 1 (0)

ICGON = 1 â â

â â (1)

ICGS = 0 us â us uc â (0)

ECGON = 0 0

(0)

ECGS = 0 us â us us â

(0)

IOFF = 1 â 1* (1) 1 (1)

(1)

â uw

EOFF = 1 â 1* (1) 0 (1) â

(1)

N = written (0) (0) (0) â â

TRIM = written (0) (0) (0) â â

â Register bit is unaffected by the given condition.

0, 1 Register bit is forced clear or set, respectively, in the given condition.

0*, 1* Register bit is temporarily forced clear or set, respectively, in the given condition.

(0), (1) Register bit must be clear or set, respectively, for the given condition to occur.

us, uc, uw Register bit cannot be set, cleared, or written, respectively, in the given condition.

6.7.1 ICG Control Register

The ICG control register (ICGCR) contains the control and status bits for the internal clock generator,

external clock generator, and clock monitor as well as the clock select and interrupt enable bits.

Address: $0036

Bit 7

Bit 0

Read:

CMF

ICGS

ECGS

CMIE

CMON

ICGON

ECGON

Write:

Reset:

= Unimplemented

Figure 6-12. ICG Control Register (ICGCR)

CMIE â Clock Monitor Interrupt Enable Bit

This read/write bit enables clock monitor interrupts. An interrupt will occur when both CMIE and CMF

are set. CMIE can be set when the CMON bit has been set for at least one cycle. CMIE is forced clear

when CMON is clear or during reset.

1 = Clock monitor interrupts enabled

0 = Clock monitor interrupts disabled

MC68HC908RK2 Data Sheet, Rev. 5.1

Freescale Semiconductor

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