MC68HC908RK2 Datasheet, PDF (129/158 Pages) Motorola, Inc – Microcontroller Unit

Table 11-2. Prescaler Selection
PS2–PS0
000
001
010
011
100
101
110
111
TIM Clock Source
Internal bus clock ÷1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
TCLK
I/O Registers
11.8.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
Register Name and Address: TCNTH—$0021
Bit 7
6
5
4
3
2
Read: Bit 15
14
13
12
11
10
Write:
Reset: 0
0
0
0
0
0
1
Bit 0
9
Bit 8
0
0
Register Name and Address: TCNTL—$0022
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-6. TIM Counter Registers (TCNTH and TCNTL)
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
129