MC68HC908RK2 Datasheet, PDF (65/158 Pages) Motorola, Inc – Microcontroller Unit

Functional Description
6.3.3.2 External Clock Input Path
The external clock input path is the means by which the microcontroller uses an external clock source.
The input to the path is the OSC1 pin and the output is the external clock (ECLK). The path, which
contains input buffering, is enabled when the ECGON bit is set and stop mode is not enabled.
6.3.4 Clock Monitor Circuit
The ICG contains a clock monitor circuit which, when enabled, will continuously monitor both the external
clock (ECLK) and the internal clock (ICLK) to determine if either clock source has failed based on these
conditions:
• Either ICLK or ECLK has stopped.
• The frequency of IBASE < frequency EREF divided by 4
• The frequency of ECLK < frequency of IREF divided by 4
Using the clock monitor requires both clocks to be active (ECGON and ICGON are both set). To enable
the clock monitor, both clocks must also be stable (ECGS and ICGS both set). This is to prevent the use
of the clock monitor when a clock is first turned on and potentially unstable
NOTE
Although the clock monitor can be enabled only when the both clocks are
stable (ICGS or ECGS is set), the clock monitor will remain enabled if one
of the clocks goes unstable.
The clock monitor only works if the external slow (EXTSLOW) bit in the
configuration register is properly defined with respect to the external
frequency source.
The clock monitor circuit, shown in Figure 6-5, contains these blocks:
• Clock monitor reference generator
• Internal clock activity detector
• External clock activity detector
6.3.4.1 Clock Monitor Reference Generator
The clock monitor uses a reference based on one clock source to monitor the other clock source. The
clock monitor reference generator generates the external reference clock (EREF) based on the external
clock (ECLK) and the internal reference clock (IREF) based on the internal clock (ICLK). To simplify the
circuit, the low-frequency base clock (IBASE) is used in place of ICLK because it always operates at or
near 307.2 kHz. For proper operation, EREF must be at least twice as slow as IBASE and IREF must be
at least twice as slow as ECLK.
To guarantee that IREF is slower than ECLK and EREF is slower than IBASE, one of the signals is divided
down. Which signal is divided and by how much is determined by the external slow (EXTSLOW) bit in the
configuration register, according to the rules in Table 6-2. Note that each signal (IBASE and ECLK) is
always divided by four. A longer divider is used on either IBASE or ECLK based on the EXTSLOW bit.
NOTE
If EXTSLOW is not set according to the rules defined in Table 6-2, the clock
monitor could switch clock sources unexpectedly.
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
65