MC68HC908RK2 Datasheet, PDF (37/158 Pages) Motorola, Inc – Microcontroller Unit

FLASH 2TS Memory
2.5.8.3 ERARNGE Routine
Name: ERARNGE
Purpose: Erase a range of addresses in FLASH memory
Entry conditions: H:X
Contains an address in the range to be erased; range size
specified by control byte
CTLBYTE Contains the erase block size in bits 5 and 6 (see Table 2-6)
DERASE Contains the erase delay time in µs/24
CPUSPD CPU frequency times 4 in MHz
Table 2-6. CTLBYTE-Erase Block Size
Bit 6
0
0
1
1
Bit 5
0
1
0
1
Block Size
Full array
One half array
Eight rows: 64 pages
Single row: 8 pages
Exit conditions: I bit
Set, masking interrupts.
This routine erases the block of FLASH defined by H:X and CTLBYTE. The algorithm defined in 2.5.3
FLASH 2TS Erase Operation is used.
Preserves the contents of H:X (address passed)
2.5.8.4 REDPROG Routine
Name: REDPROG
Purpose: This routine will use a range of multiple rows in the FLASH array to emulate
increased write/erase cycling capability of one row.
Entry conditions: H:X
Contains the address of the first row in the range. This address
must be the first address of a row (multiple of eight bytes)
LADDR Address of last row in the range; must be the first address of a
row (multiple of eight bytes)
DATA
Data to program in the row (bit 7 of DATA + 0 is used internally
and will be overwritten). Routine will always use 8 bytes starting
at DATA
BUMPS Contains the maximum allowable number of programming
bumps to use
CPUSPD Contains the bus frequency times 4 in MHz
DERASE Contains the erase delay time in µs/24
Exit conditions: C bit
Set if successful program; cleared otherwise
I bit
Set, masking interrupts
This routine uses a range of the FLASH array containing multiple rows to emulate increased write/erase
cycling capability for data storage. The routine will write data to each row of the FLASH array (in the range
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
37