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MC68HC908RK2 Datasheet, PDF (146/158 Pages) Motorola, Inc – Microcontroller Unit
Development Support
IRQ
SEE NOTE
VDD
4096 + 32 CGMXCLK CYCLES
RST
24 CGMXCLK CYCLES
Note: Any delay between rising IRQ and rising VDD will guarantee that the MCU bus is driven by the external clock.
FROM HOST
PA0
256 CGMXCLK CYCLES
(ONE BIT TIME)
1
3
1
1
2
3
1
FROM MCU
Notes: 1 = Echo delay (2 bit times)
2 = Data return delay (2 bit times)
3 = Wait 1 bit time before sending next byte.
Figure 12-13. Monitor Mode Entry Timing
MC68HC908RK2 Data Sheet, Rev. 5.1
146
Freescale Semiconductor