MC68HC908RK2 Datasheet, PDF (94/158 Pages) Motorola, Inc – Microcontroller Unit

Low-Voltage Inhibit (LVI)
8.3.1 False Trip Protection
The V_DD pin level is digitally filtered to reduce false dead battery detection due to power supply noise. For
the LVI module to reset due to a low-power supply, V_DD must remain at or below the V_LVR level for a
minimum 32–40 CGMXCLK cycles. See Table 8-1.
Table 8-1. LOWV Bit Indication
At Level:
V_DD > V_LVR
V_DD
For Number of CGMXCLK Cycles:
ANY
V_DD < V_LVR
< 32 CGMXCLK cycles
V_DD < V_LVR
V_DD < V_LVR
Between 32 & 40 CGMXCLK cycles
> 40 CGMXCLK cycles
Result
Filter counter remains clear
No reset, continue
counting CGMXCLK
LVI may generate
a reset after 32 CGMXCLK
LVI is guaranteed to generate a reset
8.3.2 Short Stop Recovery Option
The LVI has an enable time of t_EN. The system stabilization time for power-on reset and long stop
recovery (both 4096 CGMXCLK cycles) gives a delay longer than the LVI enable time for these startup
scenarios. There is no period where the MCU is not protected from a low-power condition. However, when
using the short stop recovery configuration option, the 32 CGMXCLK delay must be greater than the LVI
turn on time to avoid a period in startup where the LVI is not protecting the MCU.
NOTE
The LVI is enabled automatically after reset or stop recovery, if the
LVISTOP of the CONFIG register is set. See Chapter 3 Configuration
Register (CONFIG).
8.4 LVI Status Register
The LVI status register flags V_DD voltages below theV_LVR and V_LVS levels.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
LOWV
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
The read-only flag becomes set when the V_DD voltage falls below the V_LVR voltage for 32 to 40
CGMXCLK cycles. Reset clears the LVIOUT bit.
LOWV— LVI Low Indicator Bit
This read-only flag becomes set when the LVI is detecting V_DD voltage below the V_LVS threshold.
MC68HC908RK2 Data Sheet, Rev. 5.1
94
Freescale Semiconductor