MC68HC908RK2 Datasheet, PDF (137/158 Pages) Motorola, Inc – Microcontroller Unit

12.2.1.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
Break Module (BRK)
12.2.1.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_TST is present on the RST pin.
12.2.2 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
12.2.2.1 Wait Mode
If enabled, the break module is active in wait mode.
12.2.2.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states.
12.2.3 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register, BSCR
• Break address register high, BRKH
• Break address register low, BRKL
12.2.3.1 Break Status and Control Register
The break status and control register (BSCR) contains break module enable and status bits.
Address: $FE0E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
BRKE BRKA
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-3. Break Status and Control Register (BSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit
7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled on 16-bit address match
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine.
1 = Break address match
0 = No break address match
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
137