MC68HC908RK2 Datasheet, PDF (82/158 Pages) Motorola, Inc – Microcontroller Unit

Internal Clock Generator Module (ICG)
6.7.4 ICG DCO Divider Register
Address: $0039
Bit 7
6
5
Read:
R
R
R
Write:
Reset:
0
0
0
R = Reserved
4
3
2
1
Bit 0
R
DDIV3 DDIV2 DDIV1 DDIV0
0
U
U
U
U
U = Unaffected
Figure 6-15. ICG DCO Divider Register (ICGDVR)
DDIV3–DDIV0 — ICG DCO Divider Control Bits
These bits indicate the number of divide-by-twos (DDIV) that follow the digitally controlled oscillator.
Incrementing DDIV will add another divide-by-two, doubling the period (halving the frequency).
Decrementing has the opposite effect. DDIV cannot be written when ICGON is set to prevent
inadvertent frequency shifting. When ICGON is set, DDIV is controlled by the digital loop filter. The
range of valid values for DDIV is from $0 to $9. Values of $A–$F are interpreted the same as $9. Since
the DCO is active during reset, reset has no effect on DSTG and the value may vary.
6.7.5 ICG DCO Stage Register
Address: $003A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
DSTG7
DSTG6
DSTG5
DSTG4 DSTG3
Unaffected by reset
DSTG2
DSTG1
DSTG0
Figure 6-16. ICG DCO Stage Register (ICGDSR)
DSTG7–DSTG0 — ICG DCO Stage Control Bits
These bits indicate the number of stages DSTG (above the minimum) in the digitally controlled
oscillator. The total number of stages is approximately equal to $1FF, so changing DSTG from $00 to
$FF will approximately double the period. Incrementing DSTG will increase the period (decrease the
frequency) by 0.202% to 0.368% (decrementing has the opposite effect). DSTG cannot be written
when ICGON is set to prevent inadvertent frequency shifting. When ICGON is set, DSTG is controlled
by the digital loop filter. Since the DCO is active during reset, reset has no effect on DSTG and the
value may vary.
MC68HC908RK2 Data Sheet, Rev. 5.1
82
Freescale Semiconductor