MC68HC908RK2 Datasheet, PDF (25/158 Pages) Motorola, Inc – Microcontroller Unit

Addr. Register Name
$0027
Read:
Timer Channel 0 Register
Low (TCH0L) Write:
See page 134. _Reset:
$0028
Timer Channel 1 Status and ^Read:
Control Register (TSC1) Write:
See page 131. _Reset:
$0029
Timer Channel 1 Register ^Read:
High (TCH1H)) Write:
See page 134.
Reset:
$002A
Read:
Timer Channel 1 Register
Low (TCH1L)) Write:
See page 134. _Reset:
$002B
↓
$0035
Unimplemented
Bit 7
Bit 7
CH1F
0
0
Bit 15
Bit 7
6
6
CH1IE
0
14
6
Input/Output Section
5
4
3
2
5
4
3
2
Indeterminate after reset
0
MS1A ELS1B ELS1A
0
0
0
0
13
12
11
10
Indeterminate after reset
5
4
3
2
Indeterminate after reset
1
Bit 0
1
Bit 0
TOV1 CH1MAX
0
0
9
Bit 8
1
Bit 0
$0036
Internal Clock Generator ^Read:
Control Register (ICGCR) Write:
See page 79.
Reset:
CMIE
0
Read:
Internal Clock Generator
R
$0037 Multiplier Register (ICGMR) Write:
See page 81. _Reset:
0
$0038
Internal Clock Generator ^Read:
Trim Register (ICGTR) Write:
See page 81. _Reset:
TRIM7
1
ICG DCO Divider Control ^Read:
R
$0039
Register (ICGDVR) Write:
See page 82.
Reset: 0
$003A
ICG DCO Stage Register ^Read:
(ICGDSR) Write:
See page 82. _Reset:
DSTG7
$003B
Reserved
R
CMF
0
N6
0
TRIM6
0
R
0
DSTG6
R
CMON
0
N5
0
TRIM5
0
R
0
DSTG5
R
CS
ICGON
0
1
N4
N3
1
0
TRIM4 TRIM3
0
0
R
DDIV3
0
U
DSTG4 DSTG3
Unaffected by reset
R
R
ICGS
0
N2
1
TRIM2
0
DDIV2
U
DSTG2
R
ECGON
0
N1
0
TRIM1
0
DDIV1
U
DSTG1
R
ECGS
0
N0
1
TRIM0
0
DDIV0
U
DSTG0
R
= Unimplemented
R = Reserved U = Unaffected X = Indeterminate
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
25