MC68HC908RK2 Datasheet, PDF (115/158 Pages) Motorola, Inc – Microcontroller Unit

SIM Registers
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 10-15 shows stop mode entry timing.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 10-15. Stop Mode Entry Timing
CGMXCLK
STOP RECOVERY PERIOD
INT/BREAK
IAB
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 10-16. Stop Mode Recovery from Interrupt or Break
10.7 SIM Registers
The SIM has three memory mapped registers:
• SIM break status register, SBSR
• SIM reset status register, SRSR
• SIM break flag control register, SBFCR
10.7.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop or
wait mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
R
R
R
R
R
R
Write:
See Note
Reset:
R
= Reserved
0
Note: Writing a 0 clears SBSW.
Figure 10-17. SIM Break Status Register (SBSR)
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
115