MC68HC908RK2 Datasheet, PDF (76/158 Pages) Motorola, Inc – Microcontroller Unit

Internal Clock Generator Module (ICG)
;DDIV and DSTG modification code example
;Changes DDIV and DSTG according to the initial and
; desired clock period values
;Requires ICGON to be clear (disabled)
;User must previously calculate DVFACT and STFACT by
; the equations listed in the specification
;Modifies X and A registers
start lda
cmp
lda
add
sta
lda
store
ldx
mul
rola
rolx
bcc
rorx
inc
stx
lda
cmp
bhi
lda
sta
icgcr ;Verify ICGON clear (this will require
#13
; CMIE,CMF,CMON,ICGON,ICGS clear and CS,ECGON,ECGS set)
#dvfact ;Add the DDIV factor (calculated before
icgdvr ; coding by the DDIV2 equation)
icgdvr
#stfact ;Load the DSTG factor (calculated before coding and
; multiplied by 128 to make it 0-255 for maximum precision
icgdsr ;Load current stage register contents
;Multiply factor times current value
;Since factor was multiplied by 128,
; result is x6-x0:a7, so put it all in X
store ;If result is >255, rolx will set carry
; so divide result by two and
; add one to DDIV
icgdsr ;Store value
icgdvr ;Test to see if DDIV too high or low
#09
;Valid range 0-9; too low is FF/FE; too high is 0A/0B
exit ;If DDIV is 0-9, you’re almost done
#09
;Otherwise, maximize period and execute error code
icgdvr
Figure 6-10. Code Example for Writing DDIV and DSTG
The method of changing the unadjusted operating point is by changing the size of the capacitor. This
capacitor is designed with 639 equally sized units. 384 of which are always connected. The remaining
255 units are put in by adjusting the ICG trim factor (TRIM). The default value for TRIM is $80, or 128
units, making the default capacitor size 512. Each unit added or removed will adjust the output frequency
by about ±0.195% of the unadjusted frequency (adding to TRIM will decrease frequency). Therefore, the
frequency of IBASE can be changed to ±25% of its unadjusted value, which is enough to cancel the
process variability mentioned before.
The best way to trim the internal clock is to use the timer to measure the width of an input pulse on an
input capture pin (this pulse must be supplied by the application and should be as long or wide as
possible). Considering the prescale value of the timer and the theoretical (zero error) frequency of the bus
(307.2 kHz *N/4), the error can be calculated. This error, expressed as a percentage, can be divided by
0.195% and the resultant factor added or subtracted from TRIM. This process should be repeated to
eliminate any residual error.
NOTE
It is recommended that the user preserve a copy of the contents of the ICG
trim register (ICGTR) in non-volitale memory.
Address $7FEF is reserved for an optional factory-determined value.
Consult with a local Freescale representative for more information and
availability of this option.
MC68HC908RK2 Data Sheet, Rev. 5.1
76
Freescale Semiconductor