MC68HC908RK2 Datasheet, PDF (66/158 Pages) Motorola, Inc – Microcontroller Unit

Internal Clock Generator Module (ICG)
CMON
IBASE
ICGEN
CMON
FICGS
IBASE
ICGEN
EREF
IOFF
ICLK
ACTIVITY
DETECTOR
ICGS
IOFF
ICGS
EXTSLOW
IBASE
ICGON
EREF
EXTXTALEN
EXTSLOW
ECGS
ECGON
ECLK
DIVIDER
ESTBCLK
IREF
STOP
ECGON
ECLK
ESTBCLK
IREF
ECGEN
ECLK
ECGS
ECLK
ACTIVITY
DETECTOR
ECGS
CMON
EOFF
NAME
CONFIGURATION REGISTER BIT
NAME
NAME
TOP LEVEL SIGNAL
NAME
Figure 6-5. Clock Monitor Block Diagram
EOFF
REGISTER BIT
MODULE SIGNAL
The long divider (divide by 4096) is also used as an external crystal stabilization divider. The divider is
reset when the external clock generator is off (ECGEN is clear). When the external clock generator is first
turned on, the external clock generator stable bit (ECGS) will be clear. This condition automatically selects
ECLK as the input to the long divider. The external stabilization clock (ESTBCLK) will be ECLK divided
by 4096. This timeout allows the crystal to stabilize. The falling edge of ESTBCLK is used to set ECGS
(ECGS will set after a full 16 or 4096 cycles). When ECGS is set, the divider returns to its normal function.
ESTBCLK may be generated by either IBASE or ECLK, but any clocking will reinforce only the set
condition. If ECGS is cleared because the clock monitor determined that ECLK was inactive, the divider
will revert to a stabilization divider. Since this will change the EREF and IREF divide ratios, it is important
to turn the clock monitor off (CMON = 0) after inactivity is detected to ensure valid recovery.
MC68HC908RK2 Data Sheet, Rev. 5.1
66
Freescale Semiconductor