MC68HC908RK2 Datasheet, PDF (85/158 Pages) Motorola, Inc – Microcontroller Unit

Functional Description
ACKI
RESET
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
IRQ
V_DD
D ^CLR Q
CK
IRQ
LATCH
SYNCHRO-
NIZER
IMASKI
MODEI
HIGH
VOLTAGE
DETECT
Figure 7-2. IRQ Block Diagram
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF
IRQ
INTERRUPT
REQUEST
KEYBOARD
INTERRUPT
REQUEST
IRQ/KEYBOARD
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
Addr.
$001A
$001B
Register Name
Bit 7
6
5
IRQ and Keyboard Status Read: IRQF
and Control Register _{Write: R}
(INTKBSCR)
See page 90. ^{Reset: 0}
0
IMASKI
ACKI
0
0
Keyboard Interrupt Enable ^Read:
0
Register (INTKBIER) Write:
See page 91. _Reset:
0
KBIE6
0
KBIE5
0
= Unimplemented
4
MODEI
0
3
KEYF
R
0
2
0
ACKK
0
KBIE4 KBIE3 KBIE2
0
0
0
R = Reserved
Figure 7-3. IRQ and Keyboard I/O Register Summary
1
Bit 0
IMASKK MODEK
0
0
0
KBIE1
0
0
The IRQ pin and keyboard interrupt pins are falling-edge triggered and are software-configurable to be
both falling-edge and low-level triggered. The MODEI and MODEK bits in the INTKBSCR controls the
triggering sensitivity of the IRQ pin and keyboard interrupt pins.
When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software
clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both
of these occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch, the MODEI and MODEK
control bits, thereby clearing the interrupt even if the pin stays low.
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
85