MC68HC908RK2 Datasheet, PDF (134/158 Pages) Motorola, Inc – Microcontroller Unit

Timer Interface Module (TIM)
11.8.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Register Name and Address: TCH0H—$0026
Bit 7
6
5
4
3
2
Read:
Bit 15
14
13
12
11
10
Write:
Reset:
Indeterminate after reset
1
Bit 0
9
Bit 8
Register Name and Address: TCH0L—$0027
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
Figure 11-10. TIM Channel 0 Registers (TCH0H and TCH0L)
Register Name and Address: TCH1H—$0029
Bit 7
6
5
4
3
2
Read:
Bit 15
14
13
12
11
10
Write:
Reset:
Indeterminate after reset
1
Bit 0
9
Bit 8
Register Name and Address: TCH1L—$002A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
Figure 11-11. TIM Channel 1 Registers (TCH1H and TCH1L)
MC68HC908RK2 Data Sheet, Rev. 5.1
134
Freescale Semiconductor