MC68HC908RK2 Datasheet, PDF (136/158 Pages) Motorola, Inc – Microcontroller Unit

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IAB[15:8]
IAB[15:0]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BREAK
IAB[7:0]
Figure 12-1. Break Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
Read:
Break Address Register High
Bit 15
14
13
12
11
10
$FE0C
(BRKH) Write:
See page 138. _Reset:
0
0
0
0
0
0
Break Address Register Low ^Read: _{Bit 7}
6
5
4
3
2
$FE0D
(BRKL) Write:
See page 138. _Reset:
0
0
0
0
0
0
Break Status and Control ^Read: _BRKE
BRKA
0
0
0
0
$FE0E
Register (BSCR) Write:
See page 137.
Reset: 0
0
0
0
0
0
= Unimplemented
1
Bit 0
9
Bit 8
0
0
1
Bit 0
0
0
0
0
0
0
Figure 12-2. I/O Register Summary
12.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether module status bits can be cleared during the break
state. The BCFE bit in the SIM break flag control register (BFCR) enables software to clear status bits
during the break state. (See 10.7.3 SIM Break Flag Control Register and the Break Interrupts subsection
for each module.)
12.2.1.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
MC68HC908RK2 Data Sheet, Rev. 5.1
136
Freescale Semiconductor