MC68HC908RK2 Datasheet, PDF (101/158 Pages) Motorola, Inc – Microcontroller Unit

Port B
MCLKEN — MCLK Enable Bit
This read/write bit enables MCLK to be an output signal on PTB0. If MCLK is enabled, PTB0 is under
the control of MCLKEN. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
DDRB[5:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[5:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 9-7 shows the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
DDRBx
PTBx
PTBx
READ PTB ($0001)
Figure 9-7. Port B I/O Circuit
When bit DDRBx is a 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a 0,
reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 9-2 summarizes the operation of the port B pins.
Table 9-2. Port B Pin Functions
DDRB Bit
PTB Bit
I/O Pin Mode
0
X
Input, Hi-Z
1
X
Output
X = Don’t care
Hi-Z = High impedance
1. Writing affects data register, but does not affect input.
Accesses to DDRB
Read/Write
DDRB[7]
DDRB[5:0]
DDRB[7]
DDRB[5:0]
Accesses to PTB
Read
Write
Pin
PTB[5:0]⁽¹⁾
PTB[5:0]
PTB[5:0]
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
101