MC68HC908RK2 Datasheet, PDF (67/158 Pages) Motorola, Inc – Microcontroller Unit

Functional Description
Table 6-2. Clock Monitor Reference Divider Ratios
ICGON ECGON ECGS EXTSLOW
External
Frequency
EREF
Divider
Ratio
EREF
Frequency
ESTBCLK
Divider
Ratio
ESTBCLK
Frequency
IREF
Divider
Ratio
IREF
Frequency
0
x
x
x
u
u
u
u
u
off
0
x
0
0
x
0
off
0
off
0
u
u
x
x
0
Min 30 kHz
x
off
Max 8 MHz
0
4096 ^{1.875 kHz}
(ECLK) _{500 kHz}
1*4
76.8 kHz
±25%
x
x
1
0
Min 1 MHz
Max 8 MHz
128*4
1.953 kHz
15.63 kHz
4096
(ECLK)
244 Hz
1.953 kHz
1*4
76.8 kHz
± 25%
x
x
1
1
Min 30 kHz
1*4
Max 100 kHz
7.5 kHz
25.0 kHz
4096
(IBASE)
75 Hz
± 25%
16*4
4.8 kHz
± 25%
u: Unaffected; refer to section of table where ICGON or ECGON is set to x (don’t care)
[IBASE is always used as the internal frequency (307.2 kHz).]
6.3.4.2 Internal Clock Activity Detector
The internal clock activity detector looks for at least one falling edge on the low-frequency base clock
(IBASE) every time the external reference (EREF) is low. Since EREF is less than half the frequency of
IBASE, this should occur every time. If it does not occur two consecutive times, the internal clock inactivity
indicator (IOFF) is set. IOFF will be cleared the next time there is a falling edge of IBASE while EREF is
low.
The internal clock stable bit (ICGS) is set when IBASE is within approximately 5% of the target 307.2 kHz
±25% for two consecutive measurements. ICGS is cleared when IBASE is outside the 5% of the target
307.2 kHz ±25%, the internal clock generator is disabled (ICGEN is clear), or when IOFF is set.
6.3.4.3 External Clock Activity Detector
The external clock activity detector looks for at least one falling edge on the external clock (ECLK) every
time the internal reference (IREF) is low. Since IREF is less than half the frequency of ECLK, this should
occur every time. If it does not occur two consecutive times, the external clock inactivity indicator (EOFF)
is set. EOFF will be cleared the next time there is a falling edge of ECLK while IREF is low.
The external clock stable bit (ECGS) is also generated in the external clock activity detector. ECGS is set
on a falling edge of the external stabilization clock (ESTBCLK). This will be 4096 ECLK cycles after the
external clock generator on bit (ECGON) is set. ECGS is cleared when the external clock generator is
disabled (ECGON is clear) or when EOFF is set.
6.3.5 Clock Selection Circuit
The clock selection circuit, shown in Figure 6-6, contains two clock switches which generate the oscillator
output clock (CGMXCLK) from either the internal clock (ICLK) or the external clock (ECLK). The clock
selection circuit also contains a divide-by-two circuit which creates the clock generator output clock
(CGMOUT), which generates the bus clocks.
6.3.5.1 Clock Selection Switch
The clock select switch creates the oscillator output clock (CGMXCLK) from either the internal clock
(ICLK) or the external clock (ECLK), based on the clock select bit (CS; set selects ECLK, clear selects
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
67