MC68HC908RK2 Datasheet, PDF (135/158 Pages) Motorola, Inc – Microcontroller Unit

Chapter 12
Development Support
12.1 Introduction
This section describes the break module, the monitor read-only memory (MON), and the monitor mode
entry methods.
12.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
Features include:
• Accessible input/output (I/O) registers during break interrupts
• CPU-generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
12.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors
to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter) matches the contents of the break
address registers.
• Software writes a 1 to the BRKA bit in the break status and control register.
When a CPU-generated address matches the contents of the break address registers, the break interrupt
begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the
break routine ends the break interrupt and returns the MCU to normal operation. Figure 12-1 shows the
structure of the break module.
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
135