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MC68HC908RK2 Datasheet, PDF (150/158 Pages) Motorola, Inc – Microcontroller Unit | |||
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Electrical Specifications
13.6 3.0-Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage
(ILoad = â2.0 mA)
(ILoad = â8.0 mA)
VOH
VDD â0.3
â
VDD â1.0
â
â
V
â
Output low voltage
(ILoad = 2.0 mA)
(ILoad = 6.5 mA)
(ILoad = 5.0 mA) PTA7âPTA0 only
VOL
â
â
â
â
0.3
1.0
V
â
â
0.3
Input high voltage, all ports, IRQ, OSC1
VIH
0.7 x VDD
â
VDD + 0.3
V
Input low voltage, all ports, IRQ, OSC1
VIL
VSS
â
0.3 x VDD
V
VDD supply current
Run(3) (fop= 4.0 MHz)
Wait(4) (fop= 4.0 MHz)
Stop(5)
25 °C
â40 °C to 85 °C
25 °C with LVI enabled
â40 °C to 85 °C with LVI enabled
â
â
8.6
mA
â
â
1.2
mA
IDD
â
10
â
nA
â
â
100
nA
â
50
â
µA
â
â
350
µA
I/O ports high-impedance leakage current(6)
IIL
â1
â
+1
µA
Input current
IIn
â1
â
+1
µA
Capacitance
Ports (as input or output)
COut
CIn
â
â
â
â
12
8
pF
POR re-arm voltage(7)
VPOR
0
â
200
mV
POR reset voltage(8)
VPOR
0
700
800
mV
POR rise time ramp rate(9)
RPOR
0.02
â
â
V/ms
Monitor mode entry voltage
VTST
VDD+ 2.5
â
8
V
Pullup resistor, PTA6âPTA1, IRQ
RPU
70
â
120
kâ¦
1. Parameters are design targets at VDD = 3.0 ± 10%, VSS = 0 Vdc, TA = â40°C to +85°C, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using internal clock generator module (fop= 4.0 MHz). VDD = 3.3 Vdc. All inputs 0.2 V from
rail. No dc loads. Less than 100 pF on all outputs. All ports configured as inputs. CL = 20 pF. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using internal clock generator module, fOP = 4.0 MHz. All inputs 0.2 V from rail; no dc loads; less than
100 pF on all outputs. CL = 20 pF. OSC2 capacitance linearly affects wait IDD. All ports configured as inputs.
5. Stop IDD measured with no port pins sourcing current, all modules disabled except as noted.
6. Pullups and pulldowns are disabled.
7. Maximum is highest voltage that POR is guaranteed.
8. Maximum is highest voltage that POR is possible.
9. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
MC68HC908RK2 Data Sheet, Rev. 5.1
150
Freescale Semiconductor
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