MC68HC908RK2 Datasheet, PDF (74/158 Pages) Motorola, Inc – Microcontroller Unit

Internal Clock Generator Module (ICG)
That is, when transitioning from fast to slow:
• Going from the initial speed to half speed takes 44*N*t_ICLKFAST
• From half speed to quarter speed takes 88*N*t_ICLKFAST
• Going from quarter speed to eighth speed takes 176*N*t_ICLKFAST, and so on.
This series can be expressed as (2^x–1)*44*N*t_ICLKFAST, where x is the number of times the speed needs
doubled or halved. Since 2^x happens to be equal to τ_ICLKSLOW/τ_ICLKFAST, the equation reduces to
44*N*(τ_ICLKSLOW-τ_ICLKFAST). Note that increasing speed takes much longer than decreasing speed since
N is higher. This can be expressed in terms of the initial clock period (τ₁) minus the final clock period (τ₂)
as such:
τ₁₅ = abs[44N(τ₁ – τ₂)]
6.4.6.2 Settling to Within 5%
Once the clock period is within 15% of the desired clock period, the filter starts making smaller
adjustments. When between 15% and 5% error, each correction will adjust the clock period between
1.61% and 2.94%. In this mode, a maximum of eight corrections will be required to get to less than 5%
error. Since the clock period is relatively close to desired, each correction takes approximately the same
period of time, or 4*τ_IBASE. At this point, the internal clock stable bit (ICGS) will be set and the clock
frequency is usable, although the error will be as high as 5%. The total time to this point is:
τ₅ = abs[44N(τ₁ – τ₂)] + 32τ_IBASE
6.4.6.3 Total Settling Time
Once the clock period is within 5% of the desired clock period, the filter starts making minimum
adjustments. In this mode, each correction will adjust the frequency between 0.202% and 0.368%. A
maximum of 24 corrections will be required to get to the minimum error. Each correction takes
approximately the same period of time or 4*τ_IBASE. Added to the corrections for 15% to 5%, this makes
32 corrections (128*τ_IBASE) to get from 15% to the minimum error. The total time to the minimum error is:
τ_tot = abs[44N(τ₁ – τ₂)] + 128τ_IBASE
The equations for τ₁₅, τ₅, and τ_tot are dependent on the actual initial and final clock periods τ₁ and τ₂, not
the nominal. This means the variability in the ICLK frequency due to process, temperature, and voltage
must be considered. Additionally, other process factors and noise can affect the actual tolerances of the
points at which the filter changes modes. This means a worst case adjustment of up to 35% (ICLK clock
period tolerance plus 10%) must be added. This adjustment can be reduced with trimming. Table 6-4
shows some typical values for settling time.
Table 6-4. Typical Settling Time Examples
τ₁
1/ (6.45 MHz)
1/ (25.8 MHz)
1/ (25.8 MHz)
1/ (307.2 kHz)
τ₂
1/ (25.8 MHz)
1/ (6.45 MHz)
1/ (307.2 kHz)
1/ (25.8 MHz)
N
τ₁₅
84
430 µs
21
107 µs
1
141 µs
84
11.9 ms
τ₅
535 µs
212 µs
246 µs
12.0 ms
τ_tot
850 µs
525 µs
560 µs
12.3 ms
MC68HC908RK2 Data Sheet, Rev. 5.1
74
Freescale Semiconductor