MC68HC908RK2 Datasheet, PDF (133/158 Pages) Motorola, Inc – Microcontroller Unit

I/O Registers
NOTE
Before enabling a TIM channel register for input capture operation, make
sure that the PTB/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE
When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at 0, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100 percent. As Figure 11-9 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100 percent duty cycle level until the cycle after CHxMAX is
cleared.
OVERFLOW
OVERFLOW
PERIOD
OVERFLOW
OVERFLOW
OVERFLOW
PTBx/TCHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 11-9. CHxMAX Latency
MC68HC908RK2 Data Sheet, Rev. 5.1
Freescale Semiconductor
133