MC68HC908GZ8 Datasheet, PDF (99/344 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
Interrupts
NOTE:
VRS7–VRS0 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L
which, in conjunction with E (See 7.3.3 PLL Circuits, 7.3.6 Programming the
PLL, and 7.5.1 PLL Control Register.), controls the hardware center-of-range
frequency, f_VRS. VRS7–VRS0 cannot be written when the PLLON bit in the
PCTL is set. (See 7.3.7 Special Programming Exceptions.) A value of $00 in
the VCO range select register disables the PLL and clears the BCS bit in the
PLL control register (PCTL). (See 7.3.8 Base Clock Selector Circuit and
7.3.7 Special Programming Exceptions.). Reset initializes the register to $40
for a default range multiply value of 64.
The VCO range select bits have built-in protection such that they cannot be written
when the PLL is on (PLLON = 1) and such that the VCO clock cannot be selected
as the source of the base clock (BCS = 1) if the VCO range select bits are all clear.
The PLL VCO range select register must be programmed correctly. Incorrect
programming can result in failure of the PLL to achieve lock.
7.6 Interrupts
NOTE:
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL
can generate a CPU interrupt request every time the LOCK bit changes state. The
PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL.
PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled
or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and
PLLF reads as logic 0.
Software should read the LOCK bit after a PLL interrupt request to see if the
request was due to an entry into lock or an exit from lock. When the PLL enters
lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT
source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock
frequency is corrupt, and appropriate precautions should be taken. If the
application is not frequency sensitive, interrupts should be disabled to prevent PLL
interrupt service routines from impeding software performance or from exceeding
stack limitations.
Software can select the CGMVCLK divided by two as the CGMOUT source even
if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL
is locked before setting the BCS bit.
7.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes.
7.7.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and PLLON bits
MC68HC908GZ8
Freescale Semiconductor
Clock Generator Module (CGM)
Data Sheet
99