MC68HC908GZ8 Datasheet, PDF (136/344 Pages) Motorola, Inc – Microcontrollers

External Interrupt (IRQ)
RESET
ACK
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
IRQ
V_DD
D ^CLR Q
CK
SYNCHRONIZER
IMASK
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQF
IRQ
INTERRUPT
REQUEST
MODE
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 12-1. IRQ Module Block Diagram
NOTE:
When an interrupt pin is both falling-edge and low-level triggered, the interrupt
remains set until both of these events occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt pin returns
to logic 1. As long as the pin is low, the interrupt request remains pending. A reset
will clear the latch and the MODE control bit, thereby clearing the interrupt even if
the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A
latched interrupt request is not presented to the interrupt priority logic unless the
IMASK bit is clear.
The interrupt mask (I) in the condition code register (CCR) masks all interrupt
requests, including external interrupt requests.
Addr.
Register Name
Bit 7
6
5
IRQ Status and Control Reg- ^Read:
0
0
0
$001D
ister (INTSCR) Write:
See page 138. _Reset:
0
0
0
= Unimplemented
4
3
0
IRQF
0
0
Figure 12-2. IRQ I/O Register Summary
2
1
Bit 0
0
ACK
IMASK MODE
0
0
0
Data Sheet
136
External Interrupt (IRQ)
MC68HC908GZ8
Freescale Semiconductor