MC68HC908GZ8 Datasheet, PDF (226/344 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
19.4.2.4 Idle Characters
For TXINV = 0 (output not inverted), a transmitted idle character contains all logic
1s and has no start, stop, or parity bit. Idle character length depends on the M bit
in SCC1. The preamble is a synchronizing idle character that begins every
transmission.
If the TE bit is cleared during a transmission, the TxD pin becomes idle after
completion of the transmission in progress. Clearing and then setting the TE bit
during a transmission queues an idle character to be sent after the character
currently being transmitted.
NOTE:
When queueing an idle character, return the TE bit to logic 1 before the stop bit of
the current character shifts out to the TxD pin. Setting TE after the stop bit appears
on TxD causes data previously written to the SCDR to be lost. A good time to toggle
the TE bit for a queued idle character is when the SCTE bit becomes set and just
before writing the next byte to the SCDR.
19.4.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in ESCI control register 1 (SCC1) reverses the
polarity of transmitted data. All transmitted values including idle, break, start,
and stop bits, are inverted when TXINV is at logic 1. See 19.8.1 ESCI Control
Register 1.
19.4.2.6 Transmitter Interrupts
These conditions can generate CPU interrupt requests from the ESCI transmitter:
• ESCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the
SCDR has transferred a character to the transmit shift register. SCTE can
generate a transmitter CPU interrupt request. Setting the ESCI transmit
interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate
transmitter CPU interrupt requests.
• Transmission complete (TC) — The TC bit in SCS1 indicates that the
transmit shift register and the SCDR are empty and that no break or idle
character has been generated. The transmission complete interrupt enable
bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt
requests.
19.4.3 Receiver
Figure 19-5 shows the structure of the ESCI receiver. The receiver I/O registers
are summarized in Figure 19-2.
Data Sheet
226
Enhanced Serial Communications Interface (ESCI) Module
MC68HC908GZ8
Freescale Semiconductor