MC68HC908GZ8 Datasheet, PDF (231/344 Pages) Motorola, Inc – Microcontrollers

Enhanced Serial Communications Interface (ESCI) Module
Functional Description
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 19-7, the receiver counts 154
RT cycles at the point when the count of the transmitting device is 9 bit
times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit character with no errors is:
1----5---4-----–_{-----1---4---7-- × 100 = 4.54%}
154
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 19-7, the receiver counts 170
RT cycles at the point when the count of the transmitting device is 10 bit
times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is:
1----7---0-----–_{-----1---6---3-- × 100 = 4.12%}
170
Fast Data Tolerance
Figure 19-8 shows how much a fast received character can be misaligned
without causing a noise error or a framing error. The fast stop bit ends at RT10
instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and
RT10.
STOP
IDLE OR NEXT CHARACTER
RECEIVER
RT CLOCK
DATA
SAMPLES
Figure 19-8. Fast Data
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 19-8, the receiver counts 154
RT cycles at the point when the count of the transmitting device is
10 bit times × 16 RT cycles = 160 RT cycles.
MC68HC908GZ8
Freescale Semiconductor
Enhanced Serial Communications Interface (ESCI) Module
Data Sheet
231